1. Field of the Invention
The present invention relates to electrostatic discharge ESD protection in integrated circuits.
2. Description of Related Art
Integrated circuits have electrostatic discharge circuits coupled to input/output pads. A representative prior art electrostatic discharge protection circuit is described in Salling et al., U.S. Pat. No. 6,858,902, entitled EFFICIENT ESD PROTECTION WITH APPLICATION FOR LOW CAPACITANCE I/O PADS.
As shown in FIG. 4 of Salling et al., one prior art ESD circuit includes a diode between the pad and the supply potential VDD which leaks ESD events that have a high positive voltage to VDD limiting high voltage operation. The ESD circuit also has a field effect transistor between the pad and ground, with the parasitic bipolar transistor or silicon controlled rectifier SCR structure. The field effect transistor and parasitic bipolar transistor/SCR structure have a trigger voltage at which they turn on and discharge the electrostatic event.
It is desirable to provide ESD circuits that have a consistent trigger voltage, which turn on quickly in response to electrostatic discharge events, can handle high voltage operation and are usable with input/output pads on integrated circuits.